SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time Base Period Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 000Ah |
| EPWM1 | 2301 000Ah |
| EPWM2 | 2302 000Ah |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TBPRD | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBPRD | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | TBPRD | R/W | 0h | These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register In this case, the active register will be loaded from the shadow register when the time-base counter equals zero [b] If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware [c] The active and shadow registers share the same memory map address |