SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IrDA modes only. The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length method of frame closing is used.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0028h |
| UART1 | 0281 0028h |
| UART2 | 0282 0028h |
| UART3 | 0283 0028h |
| UART4 | 0284 0028h |
| UART5 | 0285 0028h |
| UART6 | 0286 0028h |
| WKUP_UART0 | 2B30 0028h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TXFLL | |||||||
| W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:0 | TXFLL | W | 0h | LSB register used to specify the frame length Reset Source: mod_g_arstn |