SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ASRC module is based on a single asynchronous reset that is synchronized to ASRC_SYS_CLK, ASRC_VBUS_CLK, and divider clocks (muxed version of TX and RX SYNC signals). The reset impacts configuration and processing information.
Additionally, each processing path enters a reset state when it is disabled, until the path is enabled with a new stream. This reset clears the data path and all memories associated with the path, when the new stream is started.