SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Data bus tracing selection
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| Instance Name | Physical Address |
|---|---|
| MCRC64_0 | 3030 0140h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MEN | DTC_MEN | ITC_MEN | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 1h | 1h | 1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED | NONE | 0h | Reserved |
| 2 | MEN | R/W | 1h | Enable/disables the tracing of VBUSM 0: Tracing of VBUSM controller bus has been disabled 1: Tracing of VBUSM controller bus has been enabled |
| 1 | DTC_MEN | R/W | 1h | Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled |
| 0 | ITC_MEN | R/W | 1h | Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses. |