SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
In Figure 12-292 the ECAP operating mode is almost the same as in previous section except Capture events are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle information: Period1 = T1 + T2, Period2 = T3 + T4, …etc Duty Cycle1 (on-time %) = T1 / Period1 × 100%, etc Duty Cycle1 (off-time %) = T2 / Period1 × 100%, etc.
During initialization, you must write to the active registers for both period and compare. This will then automatically copy the init values into the shadow values. For subsequent compare updates, that is, during run-time, only the shadow registers must be used.
Figure 12-292 Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect| Register | Bit | Value |
|---|---|---|
| ECCTL1 | CAP1POL | EC_RISING |
| ECCTL1 | CAP2POL | EC_FALLING |
| ECCTL1 | CAP3POL | EC_RISING |
| ECCTL1 | CAP4POL | EC_FALLING |
| ECCTL1 | CTRRST1 | EC_DELTA_MODE |
| ECCTL1 | CTRRST2 | EC_DELTA_MODE |
| ECCTL1 | CTRRST3 | EC_DELTA_MODE |
| ECCTL1 | CTRRST4 | EC_DELTA_MODE |
| ECCTL1 | CAPLDEN | EC_ENABLE |
| ECCTL1 | PRESCALE | EC_DIV1 |
| ECCTL2 | CAP_APWM | EC_CAP_MODE |
| ECCTL2 | CONT_ONESHT | EC_CONTINUOUS |
| ECCTL2 | SYNCO_SEL | EC_SYNCO_DIS |
| ECCTL2 | SYNCI_EN | EC_DISABLE |
| ECCTL2 | TSCTRSTOP | EC_RUN |