SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IrDA modes only. The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes, then program RXFLL and RXFLH to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are due to frame format with CRC and stop flag; there are two bytes associated with the FIR stop flag).
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0030h |
| UART1 | 0281 0030h |
| UART2 | 0282 0030h |
| UART3 | 0283 0030h |
| UART4 | 0284 0030h |
| UART5 | 0285 0030h |
| UART6 | 0286 0030h |
| WKUP_UART0 | 2B30 0030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RXFLL | |||||||
| W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:0 | RXFLL | W | 0h | LSB register used to specify the frame length in reception Reset Source: mod_g_arstn |