SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
U1/U2 LFPS Rx Timer Register - Link Layer Register for U1/U2 LFPS RX Timers. - This register is common for all SS ports.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 D000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_16_31 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_16_31 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| U1U2_LFPS_EXIT_RX_CLK | |||||||
| R/W | |||||||
| 1Fh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| U1U2_EXIT_RSP_RX_CLK | |||||||
| R/W | |||||||
| 1Fh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED_16_31 | R/W | 0h | Reserved |
| 15:8 | U1U2_LFPS_EXIT_RX_CLK | R/W | 1Fh | Programmable U1U2 LFPS EXIT RX CLKS - Applicable to Remote Partner initiated Ux exit: Time to recognize valid Ux exit request from the remote partner. - This field is encoded as the pipe clk [8ns] count for the LFPS. -- 1: 8ns -- 2: 16ns -- 3: 24ns, and so on Reset Source: rst_mod_g_rst_n |
| 7:0 | U1U2_EXIT_RSP_RX_CLK | R/W | 1Fh | Programmable U1U2 EXIT RESP RX CLKS - Applicable to locally initiated Ux exit: Minimum LFPS reception from remote to consider Ux exit handshake is successful. - This field is encoded as the pipe clk [8ns] count for the LFPS. -- 1: 8ns -- 2: 16ns -- 3: 24ns, and so on Reset Source: rst_mod_g_rst_n |