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SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.7.1.4.2.10 MLBDIM_CFG_MIEN Register

4.2.10.1 MLBDIM_CFG_MIEN Register (Offset = 2Ch) [reset = 0h]

See reference [R1].

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Table 14-11390 Instance Table

Instance Name	Physical Address
MLB0	02F8 202Ch

Figure 14-5642 mlbdim_cfg_MIEN Name Register

31	30	29	28	27	26	25	24
RSV2		CTX_BREAK	CTX_PE	CTX_DONE	CRX_BREAK	CRX_PE	CRX_DONE
R/W		R/W	R/W	R/W	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
RSV1	ATX_BREAK	ATX_PE	ATX_DONE	ARX_BREAK	ARX_PE	ARX_DONE	SYNC_PE
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
RSV0
R/W
0h
7	6	5	4	3	2	1	0
RSV0						ISOC_BUFO	ISOC_PE
R/W						R/W	R/W
0h						0h	0h

Table 14-11391 mlbdim_cfg_MIEN Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RSV2	R/W	0h	Reserved (write default value) Reset Source: prst_n
29	CTX_BREAK	R/W	0h	Control Tx break enable. When set, a ReceiverBreak response received from the receiver on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
28	CTX_PE	R/W	0h	Control Tx protocol error enable. When set, a ProtocolError generated by the receiver on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
27	CTX_DONE	R/W	0h	Control Tx packet done enable. When set, a packet transmitted with no errors on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
26	CRX_BREAK	R/W	0h	Control Rx break enable. When set, a ControlBreak command received from the transmitter on a control Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
25	CRX_PE	R/W	0h	Control Rx protocol error enable. When set, a packet received with no errors on a control Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
24	CRX_DONE	R/W	0h	Control Rx packet done enable. When set, a packet received with no errors on a control Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
23	RSV1	R/W	0h	Reserved (write default value) Reset Source: prst_n
22	ATX_BREAK	R/W	0h	Asynchronous Tx break enable. When set, a ReceiverBreak response received from the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
21	ATX_PE	R/W	0h	Asynchronous Tx protocol error enable. When set, a ProtocolError generated by the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
20	ATX_DONE	R/W	0h	Asynchronous Tx packet done enable. When set, a packet transmitted with no errors on an asynchronous Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
19	ARX_BREAK	R/W	0h	Asynchronous Rx break enable. When set, a AsyncBreak command received from the transmitter on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
18	ARX_PE	R/W	0h	Asynchronous Rx protocol enable. When set, a ProtocolError detected on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
17	ARX_DONE	R/W	0h	Asynchronous Rx packet done enable. When set, a packet received with no errors on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
16	SYNC_PE	R/W	0h	Synchronous protocol error enable. When set, a ProtocolError detected on a synchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n
15:2	RSV0	R/W	0h	Reserved (write default value) Reset Source: prst_n
1	ISOC_BUFO	R/W	0h	Isochronous Rx buffer overflow enable. When set, a buffer overflow on an isochronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. This occurs only when isochronous flow control is disabled. Reset Source: prst_n
0	ISOC_PE	R/W	0h	Isochronous Rx protocol error enable. When set, a ProtocolError detected on an isochronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. Reset Source: prst_n