SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Determines how long the IPOR generated by IORET entry/exit wakeup monitoring will be asserted
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 A364h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTRN_POR_DUR_IPOR_LEN_PROXY | |||||||
| R/W | |||||||
| 20h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | INTRN_POR_DUR_IPOR_LEN_PROXY | R/W | 20h | Specifies the number of HFOSC0 clock cycles to assert IPORz (low) when the wake monitoring logic detects a wakeup event. This value must exceed the minimum PORz period for the device with stable power supplies and reference clocks (1200 ns) Reset Source: mod_por_rst_n |