SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 3FA4h |
| C7X256V0_DEBUG | 0007 3400 AFA4h |
| C7X256V0_DEBUG | 0007 3400 BFA4h |
| C7X256V1_DEBUG | 0007 3800 3FA4h |
| C7X256V1_DEBUG | 0007 3800 AFA4h |
| C7X256V1_DEBUG | 0007 3800 BFA4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLAIMCLR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | CLAIMCLR | R/W | 0h | The value present reflects the current setting of the Claim Tag. |