SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Trace Status Register This register is used to establish whether the Matlock Encode Hardware is no longer queuing trace packets in the respective trace streams and also the status of the respective trace queues (whether empty or not). It can also be used to determine if trace capture is currently active or not for any of the trace queues. When a trace stream is being disabled from the enabled state, due to a trigger or ownership loss or disabling the enable bit for the trace stream or clearing the enable bit in export control register, any partially built trace packets must be drained into the respective trace queue. When the partially built trace packets have been drained then the respective done bits shall be set. The respective FIFO empty bits shall only be set when all trace data has been passed from Matlock Encode Hardware to the Matlock Export Block. The statuses available in this register are for debug purposes only and not required in any programming model.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 2010h |
| C7X256V1_DEBUG | 0007 3800 2010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_3 | DATA_TRACE_DATA_LOSS | PC_TRACE_DATA_LOSS | TIMING_TRACE_DATA_LOSS | EMULATABLE_CODE_STATUS | PLF_STATUS | EVENT_TRACE_CAPTURE_STATUS | |
| R/W | R | R | R | R | R | R | |
| 0h | 0h | 0h | 0h | 0h | 3h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EVENT_TRACE_CAPTURE_STATUS | DATA_TRACE_CAPTURE_STATUS | TIMING_TRACE_CAPTURE_STATUS | PC_TRACE_CAPTURE_STATUS | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RD_DATA_SCOREBOARD_EMPTY | TIMING_STREAM_DONE | DATA_STREAM_DONE | PC_STREAM_DONE | TIMING_FIFO_EMPTY | DATA_FIFO_EMPTY | PC_FIFO_EMPTY |
| R/W | R | R | R | R | R | R | R |
| 0h | 1h | 1h | 1h | 1h | 1h | 1h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_3 | R/W | 0h | reserved |
| 30 | DATA_TRACE_DATA_LOSS | R | 0h | Set to one by a data trace gap packet being generated Reset by Writing a 1 to TRC_CNTL:DLOST_CLR or when all data trace related streams are disabled [ie memory read, write, streaming buffer and event trace] and then one or more of them are re-enabled indicating a new trace session A loss of ownership also causes this status bit to be reset A simultaneous set and reset causes the bit to be set |
| 29 | PC_TRACE_DATA_LOSS | R | 0h | Set to one by a PC trace gap packet being generated Reset by Writing a 1 to TRC_CNTL:PLOST_CLR or a zero to one transition on TRC_CNTL:STREAM_EN [PC Trace] or a loss of ownership A simultaneous set and reset causes the bit to be set |
| 28 | TIMING_TRACE_DATA_LOSS | R | 0h | Set to one by a timing trace gap packet being generated Reset by Writing a 1 to TRC_CNTL:TLOST_CLR or a zero to one transition on TRC_CNTL:STREAM_EN [Timing Trace] or a loss of ownership A simultaneous set and reset causes the bit to be set |
| 27 | EMULATABLE_CODE_STATUS | R | 0h | The status of whether we are in untraceable secure code or not |
| 26:25 | PLF_STATUS | R | 3h | The pipeline flattener status |
| 24:23 | EVENT_TRACE_CAPTURE_STATUS | R | 0h | These bits indicate whether any data is being captured for a particular event trace mode This status accounts for all conditions [ie triggers, CPU states, trace enables and security] required to ascertain whether event trace can be collected or not |
| 22:18 | DATA_TRACE_CAPTURE_STATUS | R | 0h | This status accounts for triggers, stream enables, enable bit in Trace Export Control Register and PLF conditions and security Bit 22 Streaming Buffer Bit 21 Read Data Bit 20 Read Address Bit 19 Write Data Bit 18 Write Address |
| 17 | TIMING_TRACE_CAPTURE_STATUS | R | 0h | This status accounts for triggers, stream enables, enable bit in the trace export control register and PLF conditions and security |
| 16 | PC_TRACE_CAPTURE_STATUS | R | 0h | This status accounts for triggers, stream enables, enable bit in the trace export control register and PLF conditions and security |
| 15:7 | RESERVED | R/W | 0h | reserved |
| 6 | RD_DATA_SCOREBOARD_EMPTY | R | 1h | RD_DATA_SCOREBOARD_EMPTY status |
| 5 | TIMING_STREAM_DONE | R | 1h | TIMING_STREAM_DONE status |
| 4 | DATA_STREAM_DONE | R | 1h | DATA_STREAM_DONE status |
| 3 | PC_STREAM_DONE | R | 1h | PC_STREAM_DONE status |
| 2 | TIMING_FIFO_EMPTY | R | 1h | TIMING_FIFO_EMPTY status |
| 1 | DATA_FIFO_EMPTY | R | 1h | DATA_FIFO_EMPTY status |
| 0 | PC_FIFO_EMPTY | R | 1h | PC_FIFO_EMPTY status |