SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Digital Watchdog Down Counter
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 50A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | DWDCNTR | ||||||
| NONE | R | ||||||
| 0h | 1FFFFFFh | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DWDCNTR | |||||||
| R | |||||||
| 1FFFFFFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DWDCNTR | |||||||
| R | |||||||
| 1FFFFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DWDCNTR | |||||||
| R | |||||||
| 1FFFFFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24:0 | DWDCNTR | R | 1FFFFFFh | The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don't have an effect. Reset Source: sms_custom_rst_mod_g_rst_n |