SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Memory Context ID Register 0 This register is used to designate the desired debug context of accesses initiated via the indirect access port mechanism. Context ID Register 0 holds the reference value for the CPU register DBGCTXT. When enabled (via DBG_INDRCT_CNTL::MEM_QUAL_DCTXT ) this register is used in conjunction with DBG_INDRCT_CTXT1 and the state of the CPU register DBGCTXT to determine if the debug context criteria for an indirect access port access is met.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0034h |
| C7X256V1_DEBUG | 0007 3800 0034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DBGCTXT_MASK | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DBGCTXT_MASK | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DBGCTXT_MASK | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DBGCTXT_MASK | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | DBGCTXT_MASK | R/W | 0h | This field is used to define the context qualification mask associated with DBG_INDRCT_CTXT0 An asserted bit means the corresponding DBGCTXT_REF bit is compared |