SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ERR_ECC_TYPE register holds the current top of stack ECC error info, this is only valid when the ecc_err_valid is set
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC1 0074h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ECC_ERR_VALID | RESERVED | ||||||
| R/W1TC | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ECC_ERR_ADR | ECC_ERR_MAC | ECC_ERR_DA1 | ECC_ERR_DA0 | ECC_ERR_DED | ECC_ERR_SEC | |
| NONE | R | R | R | R | R | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | ECC_ERR_VALID | R/W1TC | 0h | When set indicates that there is valid ECC error information available, Writing a one to this register will pop the top of the stack Reset Source: vbus_mod_g_rst_n |
| 30:6 | RESERVED | NONE | 0h | Reserved |
| 5 | ECC_ERR_ADR | R | 0h | When set indicates that there was a single error detected within the address field. Bits 0 and 1 in this register indicate whether it is single or double error. Reset Source: vbus_mod_g_rst_n |
| 4 | ECC_ERR_MAC | R | 0h | When set indicates that there was a single error detected within the MAC field. Bits 0 and 1 in this register indicate whether it is single or double error. Reset Source: vbus_mod_g_rst_n |
| 3 | ECC_ERR_DA1 | R | 0h | When set indicates that there was a single error detected within the High Data word, which is bits 127 through 64 of the data word. Bits 0 and 1 in this register indicate whether it is single or double error. Reset Source: vbus_mod_g_rst_n |
| 2 | ECC_ERR_DA0 | R | 0h | When set indicates that there was a single error detected within the Low Data word, which is bits 63 through 0 of the data word. Bits 0 and 1 in this register indicate whether it is single or double error. Reset Source: vbus_mod_g_rst_n |
| 1 | ECC_ERR_DED | R | 0h | When set indicates that there was a double error detected for the block Reset Source: vbus_mod_g_rst_n |
| 0 | ECC_ERR_SEC | R | 0h | When set indicates that there was a single error detected for the block. The fields that had single error are reported by bits 2 through 5 in this register. It is possible that single error is reported in multiple fields since the ECCM inputs are partitioned into four partitions and ECC code is separate for each partition. It is also possible that none of the fields report single error even though ecc_err_sec bit is set. This can happen if single bit error occurred on the ECC code. Reset Source: vbus_mod_g_rst_n |