SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is a status register. One register per power domain. Each register contains the status for the given power domain.
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0200h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EMUIHB | PWRBAD | PORDONE | PORZ | |||
| NONE | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | STATE | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED | NONE | 0h | Reserved |
| 11 | EMUIHB | R | 0h | Emulation Alters Domain State Reset Source: chip_rst.chip_1_rst_n |
| 10 | PWRBAD | R | 0h | Power Bad error Reset Source: chip_rst.chip_1_rst_n |
| 9 | PORDONE | R | 0h | POR Done Input Status Reset Source: chip_rst.chip_1_rst_n |
| 8 | PORZ | R | 0h | PORz output actual status Reset Source: chip_rst.chip_1_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | STATE | R | 0h | Current Power Domain State 0 Power domain is off 1 Power domain is on |