SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode, registers are implemented for each port. For more details on GUSB3PIPECTL(#n) bits, refer to section "GUSB3PIPECTLn Register" in the User Guide. Note: - GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C2C0h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHYSOFTRST | HSTPRTCMPL | U2P3OK | DISRXDETP3 | UX_EXIT_IN_PX | PING_ENHANCEMENT_EN | U1U2EXITFAIL_TO_RECOV | REQUEST_P1P2P3 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 1h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| STARTRXDETU3RXDET | DISRXDETU3RXDET | DELAYP1P2P3 | DELAYP1TRANS | SUSPENDENABLE | DATWIDTH | ||
| W | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 1h | 1h | 0h | 1h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DATWIDTH | ABORTRXDETINU2 | SKIPRXDET | LFPSP0ALGN | P3P2TRANOK | P3EXSIGP2 | LFPSFILTER | RX_DETECT_TO_POLLING_LFPS_CONTROL |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 1h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SSICEN | TX_SWING | TX_MARGIN | SS_TX_DE_EMPHASIS | ELASTIC_BUFFER_MODE | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 1h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PHYSOFTRST | R/W | 0h | USB3 PHY Soft Reset After setting this bit to '1', the software needs to clear this bit. For more information, refer to Figure "Software Resets and PHY Clock Sequencing and Requirements" in the Databook. Reset Source: rst_mod_g_rst_n |
| 30 | HSTPRTCMPL | R/W | 0h | HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default, this bit must be set to 1'b0. In compliance lab testing, the SS port link enters compliance after failing the first polling sequence after power on. Set this bit to 0, when you run compliance tests. The sequence for using this functionality is as follows: - 1. Disconnect any plugged in devices. - 2. Perform USBCMD.HCRST or power-on-chip reset. - 3. Set PORTSC.PLS=0xA. - 4. Set PORTSC.PP=0. - 5. Set GUSB3PIPECTL. HstPrtCmpl=1. This places the link into compliance state. To advance the compliance pattern, follow this sequence [toggle the set GUSB3PIPECTL. HstPrtCmpl]: - 1. Set GUSB3PIPECTL.HstPrtCmpl=0. - 2. Set GUSB3PIPECTL.HstPrtCmpl=1. This advances the link to the next compliance pattern. To exit from the compliance state perform USBCMD.HCRST or power-on-chip reset. Reset Source: rst_mod_g_rst_n |
| 29 | U2P3OK | R/W | 0h | P3 OK for SSInactive [SSIP3ok] - 0: During link state SS.Inactive, put PHY in P2 [Default] - 1: During link state SS.Inactive, put PHY in P3. Reset Source: rst_mod_g_rst_n |
| 28 | DISRXDETP3 | R/W | 0h | Disabled receiver detection in P3 [DisRxDetP3] - 0: If PHY is in P3 and controller needs to perform receiver detection, The controller performs receiver detection in P3. [Default] - 1: If PHY is in P3 and controller needs to perform receiver detection, The controller changes the PHY power state to P2 and then performs receiver detection. After receiver detection, the cores changes PHY power state to P3. Reset Source: rst_mod_g_rst_n |
| 27 | UX_EXIT_IN_PX | R/W | 0h | Ux Exit in Px [Ux_exit_in_Px] - 0: The controller does U1/U2/U3 exit in PHY power state P0 [default behavior]. - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 26 | PING_ENHANCEMENT_EN | R/W | 0h | Ping Enhancement Enable [ping_enhancement_en] When set, the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns [one mac3_clk]. This field is valid for the downstream port only. Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 25 | U1U2EXITFAIL_TO_RECOV | R/W | 0h | U1U2exitfail to Recovery [u1u2exitfail_to_recov] When set, and U1/U2 LFPS handshake fails, the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It prevents interoperability issue if the remote link does not do proper handshake. Reset Source: rst_mod_g_rst_n |
| 24 | REQUEST_P1P2P3 | R/W | 1h | Always Request P1/P2/P3 for U1/U2/U3 [request_p1p2p3] When set, the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0, and immediate Ux exit [remotely initiated, or locally initiated] happens, the controller does not request P1/P2/P3 power state change. Note: This bit must be set to '1' for Synopsys PHY. For third-party SS PHY, check with your PHY vendor. Reset Source: rst_mod_g_rst_n |
| 23 | STARTRXDETU3RXDET | W | 0h | Start Receiver Detection in U3/Rx.Detect [StartRxdetU3RxDet] If DWC_USB3_GUSB3PIPECTL_INIT[22] is set, and the link is in either U3 or Rx.Detect state, the controller starts receiver detection on the rising edge of this bit. This can only be used for Downstream ports. This bit must be set to '0' for Upstream ports. This feature must not be enabled for normal operation. If have to use this feature, contact Synopsys. Reset Source: rst_mod_g_rst_n |
| 22 | DISRXDETU3RXDET | R/W | 0h | Disable Receiver Detection in U3/Rx.Det When set, the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be used for the downstream port. This bit must be set to "0" for Upstream ports. This feature must not be enabled for normal operation. If you have to use this feature, contact Synopsys. Reset Source: rst_mod_g_rst_n |
| 21:19 | DELAYP1P2P3 | R/W | 1h | Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until [DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8] 8B10B error occurs, or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality. Reset Source: rst_mod_g_rst_n |
| 18 | DELAYP1TRANS | R/W | 1h | Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1'b1: When entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals, Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0 - 1'b0: When entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIdle and pipe3_RxValid. Note: - If you are using Synopsys PHY, contact Synopsys Customer Support for recommendation on setting this bit because it is node dependent. - If you are using a third-party SS PHY, check with your PHY vendor for recommendation on setting this bit. Reset Source: rst_mod_g_rst_n |
| 17 | SUSPENDENABLE | R/W | 0h | Suspend USB3.0 SS PHY [Suspend_en] When set, and if Suspend conditions are valid, the USB 3.0 PHY enters Suspend mode. For DRD configurations, it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set to '1', then the application must clear this bit after power-on reset. Application needs to set it to '1' after the controller initialization is completed. For all other configurations, this bit can be set to '1' during controller configuration. Reset Source: rst_mod_g_rst_n |
| 16:15 | DATWIDTH | R | 1h | PIPE Data Width [DatWidth] - 2'b00: 32 bits - 2'b01: 16 bits One clock after reset, these bits receive the value seen on the pipe3_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the coreConsultant parameter must match your PHY data width and the pipe3_DataBusWidth port. Note: 8-bit data width is not supported. Reset Source: rst_mod_g_rst_n |
| 14 | ABORTRXDETINU2 | R/W | 0h | Abort Rx Detect in U2 [AbortRxDetInU2] When set and the link state is U2, the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 13 | SKIPRXDET | R/W | 0h | Skip Rx Detect: When set, the controller skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout, then repeating the operation. Reset Source: rst_mod_g_rst_n |
| 12 | LFPSP0ALGN | R/W | 0h | LFPS P0 Align: When set, - The controller deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted one clock earlier. - The controller requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state. Currently, this bit is only used in USB 3.0 HUB with Synopsys PHY. For other USB 3.0 Host, Device, and DRD cores, this bit is not required. Reset Source: rst_mod_g_rst_n |
| 11 | P3P2TRANOK | R/W | 0h | P3 P2 Transitions OK [P3P2TranOK] When set, the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set, P0 is always entered as an intermediate state during transitions between P2 and P3, as defined in the PIPE3 Specification. According to the PIPE3 Specification, any direct transition between P3 and P2 is illegal. Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 10 | P3EXSIGP2 | R/W | 0h | P3 Exit Signal in P2 [P3ExSigP2] When this bit is set, the controller always changes the PHY power state to P2, before attempting a U3 exit handshake. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3. Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 9 | LFPSFILTER | R/W | 0h | LFPS Filter [LFPSFilt] When set, filter LFPS reception with pipe3_RxValid in PHY power state P0, that is, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted. Reset Source: rst_mod_g_rst_n |
| 8 | RX_DETECT_TO_POLLING_LFPS_CONTROL | R/W | 0h | RX_DETECT to Polling.LFPS Control - 1'b0 [Default]: Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1'b1: Disables the 400us delay to start Polling LFPS after RX_DETECT. During controller certification with third party PHY it is observed that the PHY is not able to meet the Tx AC common mode voltage active [VTX-CM-ACPP_ACTIVE <100mv] if the link starts polling within 80us from the time rx.detect is performed. To meet this VTX-CM-ACPP_ACTIVE specification, the polling must be delayed further. If the PHY does not have issue then they can set this bit to 1 which allows polling to start within 80us. Reset Source: rst_mod_g_rst_n |
| 7 | SSICEN | R/W | 0h | This field is not used. Reset Source: rst_mod_g_rst_n |
| 6 | TX_SWING | R/W | 0h | Tx Swing [TxSwing] Refer to the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 5:3 | TX_MARGIN | R/W | 0h | Tx Margin[2:0] [TxMargin] Refer to Table 5-3 of the PIPE3 Specification. Reset Source: rst_mod_g_rst_n |
| 2:1 | SS_TX_DE_EMPHASIS | R/W | 1h | Tx Deemphasis [TxDeemphasis] The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. [Refer to Table 5-3 of the PIPE3 specification.] Reset Source: rst_mod_g_rst_n |
| 0 | ELASTIC_BUFFER_MODE | R/W | 0h | Elastic Buffer Mode [ElasticBufferMode] [Refer to Table 5-3 of the PIPE3 specification.] Reset Source: rst_mod_g_rst_n |