SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configuration of debug data for observation. 0x0 or 0x7 = debug outputs are tied low, 0x1 = debug outputs are UTMI interface signals, 0x2 = debug outputs are Controller debug[31:0] output 0x3 = debug outputs are Controller debug[63:32] output, 0x4 = debug outputs are clk_gate_ctrl and debug[66:64] Controller outputs, 0x5 = debug outputs are controller logic_analyzer_trace[31:0], 0x6 = debug outputs are controller logic_analyzer_trace[63:32]
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0708h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED31_3 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED31_3 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED31_3 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED31_3 | SEL | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED31_3 | R | 0h | Reserved |
| 2:0 | SEL | R/W | 0h | selection of observed local signals Reset Source: cfg_srst_n |