SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the functional clock source for the WKUP Domain
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 A010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WKUP_CLKSEL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | WKUP_CLKSEL_CLK_SEL_PROXY | R/W | 0h | Selects Clock Source for Wakeup Domain (Device Manager and Peripherals) Field values (others are reserved): 1'b0 - CPU_MAIN_PLL15_HSDIV2_CLKOUT__PERIPHERALS_ MAIN_PLL15_HSDIV0_CLKOUT 1'b0 - MAIN_PLL15_HSDIV0_CLKOUT0 (HSM_DM_CLK) 1'b1 - CPU_AND_PERIPHERALS_MCU_PLL0_HSDIV0_CLKOUT 1'b1 - MCU_PLL0_HSDIV0_CKLOUT (MCU_SYSCLK0) Reset Source: mod_g_rst_n |