SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
All warm reset sources which trigger a device/domain warm reset are captured in the MCU_CTRL RST_CTRL This register is only reset on MCU_PORz.
The MCU_CTRL RST_SRC MCU domain CTRLMMR register is shadowed in WKUP domain CTRLMMR RST_SRC so that MAIN domain processors can read it without directly accessing other domains.
After recovery from warm reset, software can read the CTRLMMR reset source register CTRLMMR RST_SRC to identify the source of previous reset. After reading this reset source register, software must clear the register.
Reset status bits read active HIGH (1) when a particular reset is triggered.
The following reset sources, which cause MCU and MAIN domain resets, are captured in the MCU domain CTRLMMR reset source register:
When a MAIN domain processor needs to issue resets to MAIN domain on error detection they will use the WARMRESETz and PORz MMR bits defined in the WKUP domain CTRLMMR.