SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Tx Threshold Control Register For more information on - Using this register, refer to "Packet Threshold and Burst Features for High Latency Systems" section in the Databook. - Selecting values for the fields of this register, see the "TX/RX Data FIFO Sizes and TX/RX Threshold Control Register Settings" section in the User Guide. Note: - GTXTHRCFG register is not applicable for Debug Target. - GTXTHRCFG register is not applicable in USB 2.0-only mode.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C108h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31 | RESERVED_30 | USBTXPKTCNTSEL | RESERVED_28 | USBTXPKTCNT | |||
| R | R | R/W | R | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| USBMAXTXBURSTSIZE | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15 | RESERVED_14 | RESERVED_13_11 | RESERVED_10_0 | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_10_0 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_31 | R | 0h | Reserved |
| 30 | RESERVED_30 | R | 0h | Reserved |
| 29 | USBTXPKTCNTSEL | R/W | 0h | USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding: - 0: USB transmission multi-packet thresholding is disabled. the controller can start transmission on the USB after the entire [one full] packet has been fetched into the corresponding TXFIFO. - 1: USB transmission multi-packet thresholding is enabled. The controller can only start transmission on the USB after USB Transmit Packet Count amount of packets for the USB transaction [burst] are already in the corresponding TXFIFO. This mode is valid in both host and device modes. It is only used for SuperSpeed operation. Reset Source: rst_mod_g_rst_n |
| 28 | RESERVED_28 | R | 0h | Reserved |
| 27:24 | USBTXPKTCNT | R/W | 0h | USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the controller can start transmission for the corresponding USB transaction [burst]. This field is only valid when the USB Transmit Packet Count Enable field is set to one. Valid values are from 1 to 15. Note: - In device mode, if device controller does not have the TRBs for the number of packets or if it cannot fetch the TRBs because of high latency or switching between other endpoints, then it does not wait for the threshold number of packets. The threshold number of packets will be honored only when the TRBs are available in the controller for the number of packets before it starts the data fetch. - This field must be less than or equal to the USB Maximum TX Burst Size field. Reset Source: rst_mod_g_rst_n |
| 23:16 | USBMAXTXBURSTSIZE | R/W | 0h | USB Maximum TX Burst Size When UsbTxPktCntSel is one, this field specifies the Maximum Bulk OUT burst the controller can do. When the system bus is slower than the USB, TX FIFO can underrun during a long burst. User can program a smaller value to this field to limit the TX burst size that the controller can do. Host mode: It only applies to SS Bulk, Isochronous, and Interrupt OUT endpoints. Device mode: This value is not used in device mode, but users need to program a value when using the TX threshold feature to make sure that the value programmed in UsbTxPktCnt is less than this value. Valid values are from 1 to 16. Reset Source: rst_mod_g_rst_n |
| 15 | RESERVED_15 | R | 0h | Reserved_15 |
| 14 | RESERVED_14 | R | 0h | Reserved1[Rsvd/Rs] Register field must write only 0 by the application. The read value must be treated as X [unknown]. |
| 13:11 | RESERVED_13_11 | R | 0h | Reserved [Rsvd/Rs] The register field must write only 0 by the application. The read value must be treated as X [unknown]. |
| 10:0 | RESERVED_10_0 | R | 0h | Reserved for future use |