SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Contains LBIST MISR output value
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 C01Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| R5SS0_LBIST_MISR_MISR_RESULT | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| R5SS0_LBIST_MISR_MISR_RESULT | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R5SS0_LBIST_MISR_MISR_RESULT | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R5SS0_LBIST_MISR_MISR_RESULT | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | R5SS0_LBIST_MISR_MISR_RESULT | R | 0h | 32-bits of MISR value selected by misr_mux_ctl Reset Source: mod_g_rst_n |