SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Device Read Instruction Configuration Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RD_INSTR_RESV5_FLD | DUMMY_RD_CLK_CYCLES_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RD_INSTR_RESV4_FLD | MODE_BIT_ENABLE_FLD | RD_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||
| R | R/W | R | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RD_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | RD_INSTR_RESV1_FLD | DDR_EN_FLD | INSTR_TYPE_FLD | |||
| R | R/W | R | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RD_OPCODE_NON_XIP_FLD | |||||||
| R/W | |||||||
| 3h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RD_INSTR_RESV5_FLD | R | 0h | Reserved |
| 28:24 | DUMMY_RD_CLK_CYCLES_FLD | R/W | 0h | Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction. |
| 23:21 | RD_INSTR_RESV4_FLD | R | 0h | Reserved |
| 20 | MODE_BIT_ENABLE_FLD | R/W | 0h | Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes. |
| 19:18 | RD_INSTR_RESV3_FLD | R | 0h | Reserved |
| 17:16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs. |
| 15:14 | RD_INSTR_RESV2_FLD | R | 0h | Reserved |
| 13:12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0] |
| 11 | RD_INSTR_RESV1_FLD | R | 0h | Reserved |
| 10 | DDR_EN_FLD | R/W | 0h | DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands |
| 9:8 | INSTR_TYPE_FLD | R/W | 0h | Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2 and DQ3] 3 : Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]] |
| 7:0 | RD_OPCODE_NON_XIP_FLD | R/W | 3h | Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode |