SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Status of Individual DCC Modules
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 4750h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | DCC_STAT_MCU_DCC1_INTR_DONE | DCC_STAT_MCU_DCC0_INTR_DONE | |||||
| NONE | R | R | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DCC_STAT_DCC8_INTR_DONE | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DCC_STAT_DCC7_INTR_DONE | DCC_STAT_DCC6_INTR_DONE | DCC_STAT_DCC5_INTR_DONE | DCC_STAT_DCC4_INTR_DONE | DCC_STAT_DCC3_INTR_DONE | DCC_STAT_DCC2_INTR_DONE | DCC_STAT_DCC1_INTR_DONE | DCC_STAT_DCC0_INTR_DONE |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17 | DCC_STAT_MCU_DCC1_INTR_DONE | R | 0h | MCU_DCC1 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 16 | DCC_STAT_MCU_DCC0_INTR_DONE | R | 0h | MCU_DCC0 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | DCC_STAT_DCC8_INTR_DONE | R | 0h | DCC8 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 7 | DCC_STAT_DCC7_INTR_DONE | R | 0h | DCC7 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 6 | DCC_STAT_DCC6_INTR_DONE | R | 0h | DCC6 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 5 | DCC_STAT_DCC5_INTR_DONE | R | 0h | DCC5 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 4 | DCC_STAT_DCC4_INTR_DONE | R | 0h | DCC4 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 3 | DCC_STAT_DCC3_INTR_DONE | R | 0h | DCC3 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 2 | DCC_STAT_DCC2_INTR_DONE | R | 0h | DCC2 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 1 | DCC_STAT_DCC1_INTR_DONE | R | 0h | DCC1 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |
| 0 | DCC_STAT_DCC0_INTR_DONE | R | 0h | DCC0 Done Interrupt Status Field values (others are reserved): 1'b0 - CLR 1'b1 - PEND Reset Source: mod_g_rst_n |