SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the write posting bits for all writ-able functional registers
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| TIMER0 | 0240 0048h |
| TIMER1 | 0241 0048h |
| TIMER2 | 0242 0048h |
| TIMER3 | 0243 0048h |
| TIMER4 | 0244 0048h |
| TIMER5 | 0245 0048h |
| TIMER6 | 0246 0048h |
| TIMER7 | 0247 0048h |
| TIMER8 | 0248 0048h |
| TIMER9 | 0249 0048h |
| TIMER10 | 024A 0048h |
| TIMER11 | 024B 0048h |
| TIMER12 | 024C 0048h |
| TIMER13 | 024D 0048h |
| TIMER14 | 024E 0048h |
| TIMER15 | 024F 0048h |
| WKUP_TIMER0 | 2B10 0048h |
| WKUP_TIMER1 | 2B11 0048h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | W_PEND_TOWR | W_PEND_TOCR | |||||
| NONE | R | R | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| W_PEND_TCVR | W_PEND_TNIR | W_PEND_TPIR | W_PEND_TMAR | W_PEND_TTGR | W_PEND_TLDR | W_PEND_TCRR | W_PEND_TCLR |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED | NONE | 0h | Reserved |
| 9 | W_PEND_TOWR | R | 0h | Write pending for register TOWR Reset Source: mod_g_rst_n |
| 8 | W_PEND_TOCR | R | 0h | Write pending for register TOCR Reset Source: mod_g_rst_n |
| 7 | W_PEND_TCVR | R | 0h | Write pending for register TCVR Reset Source: mod_g_rst_n |
| 6 | W_PEND_TNIR | R | 0h | Write pending for register TNIR Reset Source: mod_g_rst_n |
| 5 | W_PEND_TPIR | R | 0h | Write pending for register TPIR Reset Source: mod_g_rst_n |
| 4 | W_PEND_TMAR | R | 0h | Write pending for register TMAR Reset Source: mod_g_rst_n |
| 3 | W_PEND_TTGR | R | 0h | Write pending for register TTGR Reset Source: mod_g_rst_n |
| 2 | W_PEND_TLDR | R | 0h | Write pending for register TLDR Reset Source: mod_g_rst_n |
| 1 | W_PEND_TCRR | R | 0h | Write pending for register TCRR Reset Source: mod_g_rst_n |
| 0 | W_PEND_TCLR | R | 0h | Write pending for register TCLR Reset Source: mod_g_rst_n |