SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0000h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| SDMA_ADDRESS | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SDMA_ADDRESS | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | SDMA_ADDRESS | R/W | 0h | When Host Version 4 Enable is set to 0 in the Host Control 2 register,DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register [05Fh-058h] instead of using this register to sup- port both 32-bit and 64-bit addressing. This register is re-assigned to 32-bit Block Count and then SDMA may use Auto CMD23.[1] SDMA System Address [Host Version 4 Enable = 0] This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing [i.e., after a transaction has stopped]. Reading this register during SDMA transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data posi- tion can be read from this register. The SDMA transfer waits at the every boundary specified by the SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register [003h] is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. [2] 32-bit Block Count [Host Version 4 Enable = 1] Host Controller Version 4.10 re-defines this register as 32-bit Block Count [Refer to Section 1.15 for more details about block count extension]. In version 4.00, this register may be used as 32-bit block count only for Auto CMD23 to set the argument of the CMD23 while executing Auto CMD23. The Host Controller would decrement the block count of this register every block transfer and data transfer stops when the count reaches zero. This register should be accessed only when no transaction is executing. Reading this register during data transfers may return invalid value. Reset Source: vbus_amod_g_rst_n |