SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to configure the number of bytes in a data block
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0004h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | SDMA_BUF_SIZE | XFER_BLK_SIZE | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| XFER_BLK_SIZE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:12 | SDMA_BUF_SIZE | R/W | 0h |
To perform long DMA transfer, System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System Address register.
These bits shall support when the DMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the Transfer Mode register is set to 1.
7 6 5 4 3 2 1 0 |
| 11:0 | XFER_BLK_SIZE | R/W | 0h |
This field specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an invalid value and write operations shall be ignored.
2048 512 2 1 0 |