SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register gives the status of the error interrupts
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0032h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | HOST | RESP | TUNING | ADMA | AUTO_CMD | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CURR_LIMIT | DATA_ENDBIT | DATA_CRC | DATA_TIMEOUT | CMD_INDEX | CMD_ENDBIT | CMD_CRC | CMD_TIMEOUT |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12 | HOST | R/W1TC | 0h |
Occurs when detecting ERROR in m_hresp[dma transaction]
1 Host Error 0 No Error |
| 11 | RESP | R/W1TC | 0h | Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response.
1 Response Error 0 No Error |
| 10 | TUNING | R/W1TC | 0h |
This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting
Tuning Error, Host Driver needs to abort a command executing and perform tuning.To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure.
The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Turning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error.
1 Tuning Error 0 No Error |
| 9 | ADMA | R/W1TC | 0h |
This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.
1 ADMA Error 0 No Error |
| 8 | AUTO_CMD | R/W1TC | 0h |
Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared with clearing of this bit [another implementation is also allowed].
1 Auto CMD Error 0 No Error |
| 7 | CURR_LIMIT | R/W1TC | 0h |
By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.
1 Power Fail 0 No Error |
| 6 | DATA_ENDBIT | R/W1TC | 0h |
Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.
1 Data Endbit Error 0 No Error |
| 5 | DATA_CRC | R/W1TC | 0h |
Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010.
1 Data CRC Error 0 No Error |
| 4 | DATA_TIMEOUT | R/W1TC | 0h |
Occurs when detecting one of following timeout conditions:
1. Busy Timeout for R1b, R5b type.
2. Busy Timeout after Write CRC status
3. Write CRC status Timeout
4. Read Data Timeout.
1 Data Timeout Error 0 No Error |
| 3 | CMD_INDEX | R/W1TC | 0h |
Occurs if a Command Index error occurs in the Command Response.
1 Command Index Error 0 No Error |
| 2 | CMD_ENDBIT | R/W1TC | 0h |
Occurs when detecting that the end bit of a command response is 0.
1 Command End bit Error 0 No Error |
| 1 | CMD_CRC | R/W1TC | 0h |
Command CRC Error is generated in two cases.
1. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response
2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command [Stop driving CMD line] and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.
1 Command CRC Error 0 No Error |
| 0 | CMD_TIMEOUT | R/W1TC | 0h |
Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.
1 Command Timeout Error 0 No Error |