SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 003Ch |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CMD_NOT_ISSUED | RESERVED | RESP | INDEX | ENDBIT | CRC | TIMEOUT | ACMD12_NOT_EXEC |
| R | NONE | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | RESERVED | NONE | 0h | Reserved |
| 7 | CMD_NOT_ISSUED | R | 0h |
Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
1 Not Issued 0 No Error |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | RESP | R | 0h |
This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1.
1 Auto Command Response Error 0 No Error |
| 4 | INDEX | R | 0h |
Occurs if the Command Index error occurs in response to a command.
1 Auto Command Index Error 0 No Error |
| 3 | ENDBIT | R | 0h |
Occurs when detecting that the end bit of command response is 0.
1 Auto Command End Bit Error 0 No Error |
| 2 | CRC | R | 0h |
Occurs when detecting a CRC error in the command response.
1 Auto Command CRC Error 0 No Error |
| 1 | TIMEOUT | R | 0h |
Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1, the other error status bits [D04 - D02] are meaningless.
1 Auto Command Timeout Error 0 No Error |
| 0 | ACMD12_NOT_EXEC | R | 0h |
If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits [D04 - D01] are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23
1 Not Executed 0 No Error |