SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register indicates maximum current capability for each voltage
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0048h |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 |
| VDD2_1P8V | |||||||
| R | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| VDD1_3P0V | |||||||
| R | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| VDD1_3P3V | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:40 | RESERVED | NONE | 0h | Reserved |
| 39:32 | VDD2_1P8V | R | 0h | Maximum Current for 1.8V VDD2 Reset Source: vbus_amod_g_rst_n |
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | VDD1_1P8V | R | 0h | Maximum Current for 1.8V VDD1 Reset Source: vbus_amod_g_rst_n |
| 15:8 | VDD1_3P0V | R | 0h | Maximum Current for 3.0V VDD1 Reset Source: vbus_amod_g_rst_n |
| 7:0 | VDD1_3P3V | R | 0h | Maximum Current for 3.3V VDD1 Reset Source: vbus_amod_g_rst_n |