SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to configure the number of data blocks
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0084h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| XFER_BLK_COUNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| XFER_BLK_COUNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| XFER_BLK_COUNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| XFER_BLK_COUNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | XFER_BLK_COUNT | R/W | 0h |
This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II
Transfer Mode register. Data transfer stops when the count reaches zero. Setting the block count to 0 results in no data blocks is transferred.
This register should be accessed only when no transaction is executing [i.e.,after transactions are stopped]. During data transfer, read operations on this register may return an invalid value and write operations are ignored.
00000000h - Stop Count
00000001h - 1 block
00000002h - 2 blocks
..... .....
FFFFFFFFh - 4G blocks -1.
42949 67295 3 2 1 0 |