SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to access internal buffer
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00B4h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | MSG_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | MSG_SEL | R/W | 0h | Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs before '11' Three MSGs before Reset Source: vbus_amod_g_rst_n |