SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to generate UHS-II Interrupt signals
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00CCh |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| VENDOR_SPECFIC | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | DEADLOCK_TIMEOUT | CMD_RESP_TIMEOUT | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ADMA2_ADMA3 | RESERVED | EBSY | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| UNRECOVERABLE | RESERVED | TID | FRAMING | CRC | RETRY_EXPIRED_SIG_ENA | RESP_PKT | HEADER |
| R/W | NONE | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | VENDOR_SPECFIC | R/W | 0h | Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h - Interrupt Signal is Enabled Reset Source: vbus_amod_g_rst_n |
| 26:18 | RESERVED | NONE | 0h | Reserved |
| 17 | DEADLOCK_TIMEOUT | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 16 | CMD_RESP_TIMEOUT | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 15 | ADMA2_ADMA3 | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | EBSY | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 7 | UNRECOVERABLE | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | TID | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 4 | FRAMING | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 3 | CRC | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 2 | RETRY_EXPIRED_SIG_ENA | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 1 | RESP_PKT | R/W | 0h |
Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |
| 0 | HEADER | R/W | 0h | Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register.
1 Interrupt Signal is Enabled 0 Interrupt Signal is Disabled |