SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Vendor register added for autogate sdclk, cmd11 power down timer, enhancedstrobe and eMMC hardware reset
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00F8h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 91AE40F5610h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | AUTOGATE_SDCLK | ||||||
| NONE | R/W | ||||||
| 91AE40F5610h | 0h | ||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CMD11_PD_TIMER | |||||||
| R/W | |||||||
| 1388h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CMD11_PD_TIMER | EMMC_HW_RESET | ENHANCED_STROBE | |||||
| R/W | R/W | R/W | |||||
| 1388h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED | NONE | 91AE40F5610h | Reserved |
| 16 | AUTOGATE_SDCLK | R/W | 0h | If this bit is set, SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device 1 Autogating of sdclk is Enabled 0 Autogating of sdclk is Disabled |
| 15:2 | CMD11_PD_TIMER | R/W | 1388h | cmd11 power-down timer value Reset Source: vbus_amod_g_rst_n |
| 1 | EMMC_HW_RESET | R/W | 0h | Hardware reset signal is generared for eMMC card when this bit is set
1 Drives the hardware reset pin as ZERO
(Active LOW to eMMC card)
0 Deassert the hardware reset pin |
| 0 | ENHANCED_STROBE | R/W | 0h | This bit enables the enhanced strobe logic of the Host Controller 1 Enhanced strobe is Enabled 0 Enhanced strobe is Disabled |