SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is reserved for capability indication.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0204h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 1001D2CC144h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 1001D2CC144h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CF_MUL | RESERVED | CF_VAL | |||||
| R | NONE | R | |||||
| 3h | 0h | c8h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CF_VAL | |||||||
| R | |||||||
| c8h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 1001D2CC144h | Reserved |
| 15:12 | CF_MUL | R | 3h |
Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition
for details.
Field Value Description:
0h = 0.001 MHz
1h = 0.01 MHz
2h = 0.1 MHz
3h = 1 MHz
4h = 10 MHz
Other values are reserved
4 3 |
| 11:10 | RESERVED | NONE | 0h | Reserved |
| 9:0 | CF_VAL | R | c8h | Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling. The clock frequency is calculated as ITCFVAL*ITCFMUL. For example, to encode 19.2 MHz ITCFVAL shall be C0h [= 192 decimal] and ITCFMUL shall be 2h [0.1 MHz 192 * 0.1 MHz 19.2 MHz] Reset Source: vbus_amod_g_rst_n |