SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used for passing the response of a DCMD task to software.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0248h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| LAST_RESP | |||||||
| R | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| LAST_RESP | |||||||
| R | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| LAST_RESP | |||||||
| R | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| LAST_RESP | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | LAST_RESP | R | 0h | This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31 of CQT-DBR register is cleared by CQE. Reset Source: vbus_amod_g_rst_n |