SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls the generation of Response Error Detection (RED) interrupt.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0250h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| CQRMEM | |||||||
| R/W | |||||||
| fdf9a080h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| CQRMEM | |||||||
| R/W | |||||||
| fdf9a080h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CQRMEM | |||||||
| R/W | |||||||
| fdf9a080h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CQRMEM | |||||||
| R/W | |||||||
| fdf9a080h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CQRMEM | R/W | fdf9a080h | This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated 0 = When a R1/R1b response is received, bit i in the device status is ignored The reset value of this register is set to trigger an inter-rupt on all Error type bits in the device status, as defined in Section 6.13.NOTE: Responses to CMD13 [SQS] encode the QSR,so they are ignored by this logic Reset Source: vbus_amod_g_rst_n |