SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The FLC High 'n' address defines the FLC high address for FLC range 0. The FLC range is defined by FLC_LO0>=FLCrange<FLC_HI0. This register is write protected when ~ifenable0 is set.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0128h + formula |
| RL2_0 | 2500 1128h + formula |
| RL2_2 | 2500 2128h + formula |
| RL2_3 | 2500 3128h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADR_HI_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADR_HI_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADR_HI_LSW | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | ADR_HI_LSW | R/W | 0h | The ~iadr0_hi defines the FLC high address[31:12] for the FLC to copy. The remaining bits 11:0 are assumed to be ones. |
| 11:0 | RESERVED | NONE | 0h | Reserved |