SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 1014h |
| C7X256V1_DEBUG | 0007 3800 1014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CPC | CAP_SRC | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | CPC | R | 0h | Captured PC[31:01] The PC is recorded when the trigger event specified by AET_PC_0:CAP_SRC occurs The recorded PC is the state of the PC that caused or was present when the conditions were suitable for the trigger event to be set This register is loaded continuously when the trigger event is in the inactive state Software shall only change CAP_SRC while BEND=0 and REND=0 Changing CAP_SRC at any other time will result in undefined behavior |
| 0 | CAP_SRC | R/W | 0h | AET_PC Capture Source Write 0: The contents of AET_PC will be frozen on BEND [CPU_HALT trigger event] Write 1: The contents of AET_PC will be frozen on REND [CPU_INT trigger event] |