SPRUJC6 User guide

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.3.2.3.2.62 COLUMBO_COLUMBO_REG_IAR_ADD Register

3.2.62.1 COLUMBO_COLUMBO_REG_IAR_ADD Register (Offset = 20h) [reset = 0h]

Captured PC[63:32] The PC is recorded when the trigger event specified by AET_PC:CAP_SRC occurs. The recorded PC is the state of the PC that caused or was present when the conditions were suitable for the trigger event to be set. This register is loaded continuously when the trigger event is in the inactive state.

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Table 14-8814 Instance Table

Instance Name	Physical Address
C7X256V0_DEBUG	0007 3400 1020h
C7X256V1_DEBUG	0007 3800 1020h

Figure 14-4386 COLUMBO_COLUMBO_REG_IAR_ADD Name Register

31	30	29	28	27	26	25	24
RBEND	RTEND	RESERVED_2		RUDF
R/W	R/W	R/W		R/W
0h	0h	0h		0h
23	22	21	20	19	18	17	16
STRIG	STEND	RREND	RESERVED
R/W	R/W	R/W	R/W
0h	0h	0h	0h
15	14	13	12	11	10	9	8
RESERVED						ADRS
R/W						R/W
0h						0h
7	6	5	4	3	2	1	0
ADRS
R/W
0h

Table 14-8815 COLUMBO_COLUMBO_REG_IAR_ADD Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RBEND	R/W	0h	Reset Breakpoint End Status Software reset for AET_STAT:BEND status This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 : No action Write 1 : Resets AET_STAT:BEND to a zero
30	RTEND	R/W	0h	Reset Trace End Status Software reset for AET_STAT:TEND and AET_STAT:TRIG status This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 : No action Write 1 : Resets AET_STAT:TEND and AET_STAT:TRIG to a zero
29:28	RESERVED_2	R/W	0h	reserved
27:24	RUDF	R/W	0h	Reset Counter Underflow Status Software reset for AET_STAT:UDF[n] status This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 to bit n : No action Write 1 to bit n : Resets AET_STAT:UDF[n] to a zero
23	STRIG	R/W	0h	Set Trace Trigger Software set for TRACE_TRIG trigger This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 : No action Write 1 : Generates a TRACE_TRIG trigger
22	STEND	R/W	0h	Set Trace End Software set for TRACE_END trigger This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 : No action Write 1 : Generates a TRACE_END trigger
21	RREND	R/W	0h	Reset AET Interrupt Status Software reset for AET_STAT:REND status This bit has no memory so writes of 1 are self-clearing Reads : always return 0 Write 0 : No action Write 1 : Resets AET_STAT:REND to a zero
20:10	RESERVED	R/W	0h	reserved
9:0	ADRS	R/W	0h	This 10-bit value creates the indirect register address