SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Set Register 0
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_ECC_AGGR | 0071 A180h |
| C7X256V1_ECC_AGGR | 0071 B180h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EL2_RAM_EDC_CTL_BUSSECC_ENABLE_SET | CLEC_SRAM_RAMECC_ENABLE_SET | DRU_RING_EDC_ENABLE_SET | DRU_RD_BUF_EDC_ENABLE_SET | DRU_QUEUE_EDC_ENABLE_SET | DMC_DATA_CTL_BUSECC_ENABLE_SET | DMC_TAG_CTL_BUSECC_ENABLE_SET | PMC_BUSECC_ENABLE_SET |
| R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7 | EL2_RAM_EDC_CTL_BUSSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for el2_ram_edc_ctl_bussecc_pend |
| 6 | CLEC_SRAM_RAMECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for clec_sram_ramecc_pend |
| 5 | DRU_RING_EDC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for dru_ring_edc_pend |
| 4 | DRU_RD_BUF_EDC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for dru_rd_buf_edc_pend |
| 3 | DRU_QUEUE_EDC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for dru_queue_edc_pend |
| 2 | DMC_DATA_CTL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for dmc_data_ctl_busecc_pend |
| 1 | DMC_TAG_CTL_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for dmc_tag_ctl_busecc_pend |
| 0 | PMC_BUSECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for pmc_busecc_pend |