SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Program Control Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_PBIST | 0036 016Ch |
| C7X256V1_PBIST | 0037 016Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CHK | STEP | STOP | RES | START | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | CHK | R/W | 0h | Check MISR mode Reset Source: mod_g_rst_n |
| 3 | STEP | R/W | 0h | Step / Step for emulation mode Reset Source: mod_g_rst_n |
| 2 | STOP | R/W | 0h | Stop Reset Source: mod_g_rst_n |
| 1 | RES | R/W | 0h | Resume / Emulation read Reset Source: mod_g_rst_n |
| 0 | START | R/W | 0h | Start / Time Stamp mode restart Reset Source: mod_g_rst_n |