SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CTSET system configuration register
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | IDLEMODE | RESERVED | SOFTRESET | ||||
| R | R/W | R | R/W | ||||
| 0h | 2h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 3:2 | IDLEMODE | R/W | 2h | Sets the Idle Mode for CTSET (0=Force Idle, 1=No Idle, 2=Smart Idle, 3= Smart Idle wakeup) |
| 1 | RESERVED | R | 0h | Reserved, returns 0 |
| 0 | SOFTRESET | R/W | 0h | This will reset entire CTSET, except the registers and the CFG interface. This bit is automatically cleared by hardware. Reads always return 0 |