SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface. Reading DBGTIMEHI latches the lower 32 bits of debug time value CTSET configuration register
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLAIM | RESERVED2 | ||||||
| R/W | R | ||||||
| 2h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYSEVENTCAPTEN | RESERVED1 | EVENTLEVEL | MSGMODE | STOPCAPT | STARTCAPT | RESERVED | |
| R/W | R | R/W | R/W | R/W | R/W | R | |
| 0h | 0h | 1h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | CLAIM | R/W | 2h | Claim control and status. To program any bits other than 31 : 28, CTSET ownership must be claimed using bits 31 : 28. |
| 27:8 | RESERVED2 | R | 0h | Reserved, returns 0 |
| 7 | SYSEVENTCAPTEN | R/W | 0h | When 1 the System event capture is enabled |
| 6:5 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 4 | EVENTLEVEL | R/W | 1h | 0 enables low level event detection, 1 enables high level event detection |
| 3 | MSGMODE | R/W | 0h | Message generated based on event detection, 0 is sampling window, 1 is event detection |
| 2 | STOPCAPT | R/W | 0h | Stop capturing system events from external trigger detection |
| 1 | STARTCAPT | R/W | 0h | Start capturing system events from external trigger detection |
| 0 | RESERVED | R | 0h | Reserved, returns 0 |