SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls the power clock gating feature of modules and busses
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 A280h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLKGATE_CTRL0_MAIN_SMS_NOGATE_PROXY | RESERVED | CLKGATE_CTRL0_MAIN_SA3SS_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_R5SS1_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_R5SS0_NOGATE_PROXY | RESERVED | CLKGATE_CTRL0_MAIN_PDMA7_NOGATE_PROXY |
| R/W | NONE | R/W | R/W | R/W | R/W | NONE | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLKGATE_CTRL0_MAIN_PDMA6_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA5_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA4_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA3_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA2_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA1_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_PDMA0_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_DMSS_NOGATE_PROXY |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CLKGATE_CTRL0_MAIN_AUDIO_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_IPCSS_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_MEM_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_MISC_PERI_CBA_NOGATE_PROXY | RESERVED | ||
| NONE | R/W | R/W | R/W | R/W | NONE | ||
| 0h | 0h | 0h | 1h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_DATA_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_CENTRAL_CBA_NOGATE_PROXY | CLKGATE_CTRL0_WKUP_DM_PWR_NOGATE_PROXY | CLKGATE_CTRL0_WKUP_DM_CBA_NOGATE_PROXY | CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY | |
| NONE | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 1h | 1h | 1h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLKGATE_CTRL0_MAIN_SMS_NOGATE_PROXY | R/W | 0h | MAIN domain SMS auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 30 | RESERVED | NONE | 0h | Reserved |
| 29 | CLKGATE_CTRL0_MAIN_SA3SS_NOGATE_PROXY | R/W | 0h | MAIN domain SA3SS auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 28 | CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain Debug CBASS auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 27 | CLKGATE_CTRL0_MAIN_R5SS1_NOGATE_PROXY | R/W | 0h | MAIN domain R5SS1 auto clock gate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 26 | CLKGATE_CTRL0_MAIN_R5SS0_NOGATE_PROXY | R/W | 0h | MAIN domain R5SS0 auto clock gate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 25 | RESERVED | NONE | 0h | Reserved |
| 24 | CLKGATE_CTRL0_MAIN_PDMA7_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA7 (ASRC11) auto clock gate on idle disable. Field values (others are reserved): 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 23 | CLKGATE_CTRL0_MAIN_PDMA6_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA6 (ASRC0) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled 1'b0 - Auto clock gating enabled Reset Source: mod_por_rst_n |
| 22 | CLKGATE_CTRL0_MAIN_PDMA5_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA5 (ADC) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 21 | CLKGATE_CTRL0_MAIN_PDMA4_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA4 (SPI/MCAN 1) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 20 | CLKGATE_CTRL0_MAIN_PDMA3_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA3 (McASP1) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 19 | CLKGATE_CTRL0_MAIN_PDMA2_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA2 (McASP0) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 18 | CLKGATE_CTRL0_MAIN_PDMA1_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA1 (UART) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 17 | CLKGATE_CTRL0_MAIN_PDMA0_NOGATE_PROXY | R/W | 0h | MAIN domain PDMA0 (SPI/MCAN 0) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 16 | CLKGATE_CTRL0_MAIN_DMSS_NOGATE_PROXY | R/W | 0h | MAIN domain DMSS auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 15 | RESERVED | NONE | 0h | Reserved |
| 14 | CLKGATE_CTRL0_MAIN_AUDIO_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain Infrastructure bus (AUDIO) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 13 | CLKGATE_CTRL0_MAIN_IPCSS_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain Infrastructure CBASS auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 12 | CLKGATE_CTRL0_MAIN_MEM_CBA_NOGATE_PROXY | R/W | 1h | MAIN domain infrastructure bus (MEM) auto cloclk gate on idle disable Reset Source: mod_por_rst_n |
| 11 | CLKGATE_CTRL0_MAIN_MISC_PERI_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain Infrastructure bus (Misc Peripheral) auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 10:6 | RESERVED | NONE | 0h | Reserved |
| 5 | CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain data bus auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 4 | CLKGATE_CTRL0_MAIN_DATA_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain data bus auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 3 | CLKGATE_CTRL0_MAIN_CENTRAL_CBA_NOGATE_PROXY | R/W | 1h | WKUP domain Infrastructure ECC aggregator auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 2 | CLKGATE_CTRL0_WKUP_DM_PWR_NOGATE_PROXY | R/W | 1h | WKUP domain Device Manager auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 1 | CLKGATE_CTRL0_WKUP_DM_CBA_NOGATE_PROXY | R/W | 1h | WKUP domain device manager CBA auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 0 | CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY | R/W | 0h | MAIN domain Infrastructure bus auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |