SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Event Pop Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0803 D030h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EVENT_POP | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | EVENT_POP | W | 0h | Event Pop. When a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read from the CPSW_CPTS_EVENT_0_REG to CPSW_CPTS_EVENT_3_REG registers. Popping an event discards the event and causes the next event, if any, to be moved to the top of the FIFO ready to be read by software on interrupt. |