SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The CTI implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 2000 4FB4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NTT | LOCK_STATUS | SLI | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED | R | 0h | Reserved, returns 0 |
| 2 | NTT | R | 0h | Register size Indicator. Always 0. Indiates that the LAR is implemented as 32-bit |
| 1 | LOCK_STATUS | R | 0h | The CTI implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked. Application must write to the LAREG to gain access. |
| 0 | SLI | R | 0h | Software Lock Implemented. Indicates that a lock control mechanism is present from this interface |