SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The CFG register provides information about how the MEM-AP implementation is configured.
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 4000 22F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LD | LA | BE | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED | R | 0h | Reserved bit, return 0 |
| 2 | LD | R | 0h | This bit indicates whether the MEM-AP implementation includes the Large Data Extension, that provides support for data items larger than 32-bits, it is 0 |
| 1 | LA | R | 0h | This bit indicates whether the MEM-AP implementation includes the Large Physical Address Extension, that supports physical addresses of more than 32-bits: |
| 0 | BE | R | 0h | ADIv52 obsoletes support for big-endian MEM-AP, and this bit must RAZ |