SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controller Status Register to access the internal status of HyperBus Memory Controller IP
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| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RFU3 | WRSTOERR | WTRSERR | WDECERR | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RFU2 | WACT | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RFU1 | RDSSTALL | RRSTOERR | RTRSERR | RDECERR | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFU0 | RACT | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RFU3 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 26 | WRSTOERR | R | 0h | Write RSTO error. This bit indicates whether HyperBus memory is under reset state in the latest write operation.When this bit is set, HyperBus Memory Controller IP responds by AXI SLVERR.0-Normal operation,1- HyperBus memory is under reset Reset Source: mod_g_rst_n |
| 25 | WTRSERR | R | 0h | Write Transaction Error. This bit indicates whether AXI protocol is acceptable by HyperBus Memory Controller IP in the latest write transaction.When this bit is set, HyperBus Memory Controller IP responds by AXI SLVERR.0-Normal operation,1- This protocol is not supported Reset Source: mod_g_rst_n |
| 24 | WDECERR | R | 0h | Write Decode Error. This bit indicates whether access address is acceptable in the latest write transaction.When this bit is set, HyperBus Memory Controller IP responds by AXI DECERR.0-Normal operation. 1- Access address is not reachable Reset Source: mod_g_rst_n |
| 23:17 | RFU2 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 16 | WACT | R | 0h | Write is Active. This bit indicates whether write transaction is in progress or not.0- Write is idle,1 - Write is active.When receiving write request on write address channel, this bit becomes 1. When retrieving response signaling on write response channel, this bit becomes 0. Reset Source: mod_g_rst_n |
| 15:12 | RFU1 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 11 | RDSSTALL | R | 0h | RDS Stall. This bit indicates whether read data transfer from HyperBus memory is stalled [RDS remains LOW] in the latest read transaction.When this bit is set, HyperBus Memory Controller IP responds by AXI SLVERR. Reset Source: mod_g_rst_n |
| 10 | RRSTOERR | R | 0h | Read RSTO error. This bit indicates whether HyperBus memory is under reset state in the latest read operation.When this bit is set, HyperBus Memory Controller IP responds by AXI SLVERR.0 -Normal operation, 1 -HyperBus memory is under reset Reset Source: mod_g_rst_n |
| 9 | RTRSERR | R | 0h | Read Transaction Error. This bit indicates whether AXI protocol is acceptable by HyperBus Memory Controller IP in the latest read transaction.When this bit is set, HyperBus Memory Controller IP responds by AXI SLVERR.0- Normal operation,1- This protocol is not supported Reset Source: mod_g_rst_n |
| 8 | RDECERR | R | 0h | Read Decode Error. This bit indicates whether access address is acceptable in the latest read transaction.When this bit is set, HyperBus Memory Controller IP responds by AXI DECERR.0 -Normal operation,1- Access address is not reachable Reset Source: mod_g_rst_n |
| 7:1 | RFU0 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 0 | RACT | R | 0h | Read is Active. This bit indicates whether read transaction is in progress or not. 0 - Read is idle, 1-Read is active. When receiving read request on read address channel, this bit becomes 1. When retrieving all requested data on read data channel, this bit becomes 0 Reset Source: mod_g_rst_n |