SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Memory Base Address Register for device connected to CS#
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| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4010h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| A_MSB | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| A_LSB | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| A_LSB | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| A_LSB | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | A_MSB | R/W | 0h | MSB 8 bit of the base address of addressable region to HyperBus memory Reset Source: mod_g_rst_n |
| 23:0 | A_LSB | R | 0h | Since register can be set in 16M bytes boundary, lower 24 bit is fixed to 0, if read, this field will always return 0 Reset Source: mod_g_rst_n |