SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the raw interrupt status as defined in HL0.8 for the Output FIFO interrupts. The FIFO interrupt for each channel is configured in the control register for the channel. A read of the Interrupt Status Raw / Set Register returns the current pending status of the interrupt sources with no regard to any enable settings. A write to this register sets the interrupt pending status of each interrupt source whose corresponding bit is 1 in the value written. Note that reading this register immediately after writing to it would reflect old value instead of the written value; wait for 2 system clock cycles after writing to read written value.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0034h |
| AASRC1 | 02D4 0034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHANNEL_15_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_14_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_13_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_12_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_11_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_10_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_9_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_8_OUTPUT_FIFO_THRESHOLD_RAW |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHANNEL_7_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_6_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_5_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_4_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_3_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_2_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_1_OUTPUT_FIFO_THRESHOLD_RAW | CHANNEL_0_OUTPUT_FIFO_THRESHOLD_RAW |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | R | 0h | Always read as 0 |
| 15 | CHANNEL_15_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 15 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 14 | CHANNEL_14_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 14 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 13 | CHANNEL_13_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 13 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 12 | CHANNEL_12_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 12 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 11 | CHANNEL_11_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 11 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 10 | CHANNEL_10_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 10 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 9 | CHANNEL_9_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 9 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 8 | CHANNEL_8_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 8 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 7 | CHANNEL_7_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 7 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 6 | CHANNEL_6_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 6 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 5 | CHANNEL_5_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 5 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 4 | CHANNEL_4_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 4 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 3 | CHANNEL_3_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 3 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 2 | CHANNEL_2_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 2 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 1 | CHANNEL_1_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 1 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 0 | CHANNEL_0_OUTPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Channel 0 Output FIFO Threshold Interrupt Read indicates raw status. This fires when the Output FIFO for this Channel is above the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |